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| data sheet 1 rev. 1.00 www.infineon.com 2017-08-24 BTS7040-2EPA 1 overview potential applications ? suitable for resistive, induc tive and capacitive loads ? replaces electromechanical rela ys, fuses and discrete circuits ? driving capability suitable for 3.5 a loads and high inrush current loads such as p27w + r5w lamps or led equivalent figure 1 BTS7040-2EPA application di agram. further information in chapter 10 profet tm +2 2x 40 m smart high-side power switch package pg-tsdso-14-22 marking 7040-2a gpio gpio gpio gpio a/d in vss vdd micro controller in0 in1 den dsel is gnd out0 out1 vs v bat c sense d z1 r/l cable r/l cable r/l cable c out1 c out0 r in r in r den r dsel r ad r is_prot r sense r gnd v dd r pd r pd c vs r ol t 1 d z2 app_2ch_li_intdio_cover.emf control protection diagnosis t t
data sheet 2 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 overview basic features ? high-side switch with diag nosis and embedded protection ?part of profet tm +2 family ? reversave? for low power diss ipation in reverse polarity ? switch on capability while inverse current condition (inverseon) ? green product (rohs compliant) ? qualified in accordance with aec q100 grade 1 protection features ? absolute and dynamic temperature li mitation with controlled restart ? overcurrent protection (tripping) with intelligent restart control ? undervoltage shutdown ? overvoltage protection with external components diagnostic features ? proportional load current sense ? open load in on and off state ? short circuit to ground and battery description the BTS7040-2EPA is a smart high-side power switch, providing protection func tions and diagnosis. the device is integrated in smart7 technology. table 1 product summary parameter symbol values minimum operating voltage (at switch on) v s(op) 4.1 v minimum operating voltage (cranking) v s(uv) 3.1 v maximum operating voltage v s 28 v minimum overvoltage protection ( t j = 25 c) v ds(clamp) 35 v maximum current in sleep mode ( t j 85 c) i vs(sleep) 1 a maximum operative current i gnd(active) 4 ma maximum on-state resistance ( t j = 150 c) r ds(on) 36 m nominal load current ( t a = 85 c) i l(nom) 3.5 a typical current sense ratio at i l = i l(nom) k ilis 1800 data sheet 3 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 block diagram and terms 2 block diagram and terms 2.1 block diagram figure 2 block diagram of BTS7040-2EPA in 0 esd pr otec tion + in put logic is den dsel in 1 internal power supply block_profet2ch_revon.emf gnd circuitry supply voltage monitoring overvolt age pr otec tion in telligent restart cont rol sense output vs gnd out1 out0 in ter nal re verse polar ity p rotection channel 1 t driver logic gate control + chargepump load current sense ov erte mp era t ure overvolt age clampi ng ov ercurr ent pr otec tion outp ut voltage limitation voltage sensor reversave tm in verseo n channel 0 t driver logic gate control + chargepump load current sense overtemp erature overvolt age clampi ng ov ercurr ent protection outp ut voltage limitation voltage sensor reversave tm in ve rseo n data sheet 4 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 block diagram and terms 2.2 terms figure 3 shows all terms used in this data sheet, with associated convention for positive values. figure 3 voltage and current convention i inn i den i is v s i gnd i ln i dsel inn den dsel is gnd vs outn v inn v den v dsel v is v outn v dsn i vs terms_profet.emf v sis data sheet 5 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 pin configuration 3 pin configuration 3.1 pin assignment figure 4 pin configuration vs gnd out0 in0 den is dsel in1 n.c. out0 out0 n.c. out1 out1 out1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 pinout_profet2ch.emf ex pos ed pad (bo tto m) data sheet 6 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 pin configuration 3.2 pin definitions and functions table 2 pin definition pin symbol function ep vs (exposed pad) supply voltage battery voltage 1gnd ground signal ground 2, 6 inn input channel n digital signal to switch on channel n (?high? active) if not used: connect with a 10 k resistor either to gnd pin or to module ground 3den diagnostic enable digital signal to enable device diag nosis (?high? active) and to clear the protection counter of channe l selected with dsel pin if not used: connect with a 10 k resistor either to gnd pin or to module ground 4is sense current output analog/digital signal for diagnosis if not used: left open 5dsel diagnosis selection digital signal to select one channel to perform on and off state diagnosis (?high? active) if not used: connect with a 10 k resistor either to gnd pin or to module ground 7, 11 n.c. not connected, internally not bonded 8-10, 12- 14 outn output n protected high-side power output channel n 1) 1) all output pins of the channel must be connected together on the pcb. all pins of the output are internally connected together. pcb traces have to be designed to withstand the maximum current which can flow data sheet 7 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 general product characteristics 4 general product characteristics 4.1 absolute maximum ratings - general table 3 absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground, positive cu rrent flowing into pin (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max. supply pins power supply voltage v s -0.3 ? 28 v ? p_4.1.0.1 load dump voltage v bat(ld) ? ? 35 v suppressed load dump acc. to iso16750-2 (2010). r i = 2 p_4.1.0.3 supply voltage for short circuit protection v bat(sc) 0?24vsetup acc. to aec-q100-012 p_4.1.0.25 reverse polarity voltage - v bat(rev) ??16v t 2 min t a = +25 c setup as described in chapter 10 p_4.1.0.5 current through gnd pin i gnd -50 ? 50 ma r gnd according to chapter 10 p_4.1.0.9 logic & control pins (digital input = di) di = inn, den, dsel current through di pin i di -1 ? 2 ma 2) p_4.1.0.14 current through di pin reverse battery condition i di -1 ? 10 ma 2) t 2 min p_4.1.0.36 is pin voltage at is pin v is -1.5 ? v s v i is = 10 a p_4.1.0.16 current thro ugh is pin i is -25 ? i is(sat),m ax ma ? p_4.1.0.18 temperatures junction temperature t j -40 ? 150 c ? p_4.1.0.19 storage temperature t stg -55 ? 150 c ? p_4.1.0.20 esd susceptibility data sheet 8 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 general product characteristics notes 1. stresses above the ones listed he re may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection functions are designed to preven t ic destruction under fault conditions described in the data sheet. fault conditions are cons idered as ?outside? normal operatin g range. protection functions are not designed for continuous repetitive operation. 4.2 absolute maximum ratings - power stages 4.2.1 power stage - 40 m esd susceptibility all pins (hbm) v esd(hbm) -2 ? 2 kv hbm 3) p_4.1.0.21 esd susceptibility outn vs gnd and vs connected (hbm) v esd(hbm)_ou t -4 ? 4 kv hbm 3) p_4.1.0.22 esd susceptibility all pins (cdm) v esd(cdm) -500 ? 500 v cdm 4) p_4.1.0.23 esd susceptibility corner pins (cdm) (pins 1, 7, 8, 14) v esd(cdm)_cr n -750 ? 750 v cdm 4) p_4.1.0.24 1) not subject to production test - specified by design. 2) maximum v di to be considered fo r latch-up tests: 5.5 v 3) esd susceptibility, hbm accordin g to ansi/esda/jedec js001 (1.5 k ? , 100 pf) 4) esd susceptibility, charged device model ?cdm? according jedec jesd22-c101 table 4 absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground, positive cu rrent flowing into pin (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max. maximum energy dissipation single pulse e as ??36mj i l = 2* i l(nom) t j(0) = 150 c v s = 28 v p_4.2.6.1 table 3 absolute maximum ratings 1) (continued) t j = -40 c to +150 c; all voltages with respect to ground, positive cu rrent flowing into pin (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max. data sheet 9 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 general product characteristics 4.3 functional range note: within the functional or operatin g range, the ic operates as descri bed in the circuit description. the electrical characteristics are specified within the co nditions given in the el ectrical characteristics tables. maximum energy dissipation repetitive pulse e ar ??13mj i l = i l(nom) t j(0) = 85 c v s = 13.5 v 1m cycles p_4.2.6.2 load current | i l |?? i l(ovl),m ax a? p_4.2.6.3 1) not subject to production test - specified by design. table 5 functional range - supply voltage and temperature 1) 1) not subject to production test - specified by design. parameter symbol values unit note or test condition number min. typ. max. supply voltage range for normal operation v s(nor) 6 13.5 18 v ? p_4.3.0.1 lower extended supply voltage range for operation v s(ext,low) 3.1 ? 6 v 2)3) (parameter deviations possible) 2) in case of v s voltage decreasing: v s(ext,low),min =3.1v. in case of v s voltage increasing: v s(ext,low),min =4.1v p_4.3.0.2 upper extended supply voltage range for operation v s(ext,up) 18 ? 28 v 3) (parameter deviations possible) 3) protection functions still operative p_4.3.0.3 junction temperature t j -40 ? 150 c ? p_4.3.0.5 table 4 absolute maximum ratings 1) (continued) t j = -40 c to +150 c; all voltages with respect to ground, positive cu rrent flowing into pin (unless otherwise specified) parameter symbol values unit note or test condition number min. typ. max. data sheet 10 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 general product characteristics 4.4 thermal resistance note: this thermal data was generated in accord ance with jedec jesd51 standards. for more information, go to www.jedec.org . 4.4.1 pcb setup figure 5 1s0p pcb cross section figure 6 2s2p pcb cross section table 6 thermal resistance 1) 1) not subject to production test - specified by design. parameter symbol values unit note or test condition number min. typ. max. thermal characterization parameter junction-top jtop ?2.44.1k/w 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natura l convection on fr4 2s2p board; the product (chip + package) was simulated on a 76.2 114.3 1.5 mm board with 2 inner copper layers (2 70 m cu, 2 35 m cu). where applicable a thermal via array under the exposed pad co ntacted the first inner copper layer. simulation done at t a = 105c, p dissipation = 1 w. p_4.4.0.1 thermal resistance junction-to-case r thjc ?1.62.7k/w 2) simulated at exposed pad p_4.4.0.2 thermal resistance junction-to-ambient r thja ? 31.8 ? k/w 2) p_4.4.0.3 70 m modeled (traces, cooling area) 1,5 mm 70 m, 5% metalization* pcb_zth_1s0p.emf *: means percentual cu metalization on each layer 70 m modelled (traces) 35 m, 90% metalization* 1,5 mm 70 m, 5% metalization* pcb_zth_2s2p.emf 35 m, 90% metalization* *: means percentual cu metalization on each layer data sheet 11 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 general product characteristics figure 7 pcb setup for thermal simulations figure 8 thermal vias on pcb for 2s2p pcb setup 4.4.2 thermal impedance pcb_sim _setup_tsdso14.emf pcb 1s0p + 600 mm 2 cooling pcb 2s2p / 1s0p footprint pcb_ 2s2p_vi as_t s ds o14. emf data sheet 12 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 general product characteristics figure 9 typical thermal impe dance. pcb setup according chapter 4.4.1 figure 10 thermal resistan ce on 1s0p pcb with various cooling surfaces 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 z thja (k/w) t a = 105c time (s) bts7040-2epx 2s2p 1s0p - 600 mm 1s0p - 300 mm 1s0p - footprint 30 40 50 60 70 80 90 100 110 120 130 0 100 200 300 400 500 600 r thja (k/w) cooling area (mm 2 ) bts7040-epx 1s0p - ta = 105c data sheet 13 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 logic pins 5 logic pins the device has 4 digital pins for direct control. 5.1 input pins (inn) the input pins in0, in1 activate the corresponding outp ut channel. the input circuitry is compatible with 3.3v and 5v micro controller. the electrical equi valent of the input circuitry is shown in figure 11 . in case the pin is not used, it must be connected with a 10 k resistor either to gnd pin or to module ground. figure 11 input circuitry the logic thresholds for ?low? and ?hig h? states are defined by parameters v di(th) and v di(hys) . the relationship between these two values is shown in figure 12 . the voltage v in needed to ensure a ?high? state is always higher than the voltage need ed to ensure a ?low? state. figure 12 input threshold voltages and hysteresis gnd in i gn d i di v di input_in_intdio.emf vs v s(clamp ) r gnd i di esd v di (clamp) input_vdith_2.emf v di(th ),max v di(hys) t v di v di(th ),min internal channel activation signal t 0 x 1 x 0 v di(th) data sheet 14 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 logic pins 5.2 diagnosis pin the diagnosis enable (den) pin contro ls the diagnosis circuitry and the pr otection circuitry. when den pin is set to ?high?, the diagnosis is enabled (see chapter 9.2 for more details). when it is set to ?low?, the diagnosis is disabled (is pin is set to high impedance). the diagnosis selection (dsel) pin selects th e channel where diagnosis is performed (see chapter 9.1.1 ). the transition from ?high? to ?low? of den pin clears the protection latc h of the channel selected with dsel pin depending on the logic state of in pin and den pulse length (see chapter 8.3 for more details). the internal structure of diagnosis pins is the same as the one of input pins. see figure 11 for more details. data sheet 15 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 logic pins 5.3 electrical characteristics logic pins v s = 6 v to 18 v, t j = -40 c to +150 c typical values: v s = 13.5 v, t j = 25 c digital input (di) pins = in, den, dsel table 7 electrical characteri stics: logic pins - general parameter symbol values unit note or test condition number min. typ. max. digital input voltage threshold v di(th) 0.8 1.3 2 v see figure 11 and figure 12 p_5.4.0.1 digital input clamping voltage v di(clamp1) ?7?v 1) i di = 1 ma see figure 11 and figure 12 1) not subject to production test - specified by design p_5.4.0.2 digital input clamping voltage v di(clamp2) 6.5 7.5 8.5 v i di = 2 ma see figure 11 and figure 12 p_5.4.0.3 digital input hysteresis v di(hys) ?0.25?v 1) see figure 11 and figure 12 p_5.4.0.4 digital input current (?high?) i di 21025a v di = 2 v see figure 11 and figure 12 p_5.4.0.5 digital input current (?low?) i di 21025a v di = 0.8 v see figure 11 and figure 12 p_5.4.0.6 data sheet 16 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power supply 6 power supply the BTS7040-2EPA is supplied by v s , which is used for the internal logic as well as supply for the power output stages. v s has an undervoltage detection circuit, which preven ts the activation of the power output stages and diagnosis in case the applied voltage is below the undervoltage threshold. 6.1 operation modes BTS7040-2EPA has the foll owing operation modes: ?sleep mode ?active mode ?stand-by mode the transition between operation modes is determined according to these variables: ? logic level at inn pins ? logic level at den pin the state diagram including the po ssible transitions is shown in figure 13 . the behavior of BTS7040-2EPA as well as some parameters may change in dependence from the operation mode of the device. furthermore, due to the undervoltage detect ion circuitry which monitors v s supply voltage, some changes within the same operation mode can be seen accordingly. there are three parameters describing each operation mode of BTS7040-2EPA: ? status of the output channel ? status of the diagnosis ? current consumption at vs pin (measured by i vs in sleep mode, i gnd in all other operative modes) table 8 shows the correlation between operation modes, v s supply voltage, and the state of the most important functions (channel status, diagnosis). figure 13 operation mode state diagram powersupply_opmode_profet.emf sleep active in = ?hig h? in = ?low? & den = ?high? stand-by in = ?low ? & den = ?low? power-up in = ?low? & den = ?high? in = ?low ? & den = ?low? v s > v s(op) unsupplied in = ?high? den = ?high? den = ?low? data sheet 17 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power supply 6.1.1 unsupplied in this state, the device is either unsupplied (no voltage applied to vs pin) or the supply voltage is below the undervoltage threshold. 6.1.2 power-up the power-up condition is ente red when the supply voltage ( v s ) is applied to the device. the supply is rising until it is above the undervoltage threshold v s(op) therefore the internal power-on signals are set. 6.1.3 sleep mode the device is in sleep mode when all digital input pins (inn, den, dsel) are set to ?low?. when BTS7040-2EPA is in sleep mode, all outputs are off. the current consumption is minimum (see parameter i vs(sleep) ). no overtemperature or overload protecti on mechanism is active when the de vice is in sleep mode. the device can go in sleep mode only if the protec tion is not active (counter = 0, see chapter 8.3.1 for further details). 6.1.4 stand-by mode the device is in stand-by mode as long as den pin is se t to ?high? while input pins are set to ?low?. all channels are off therefore only open load in off diagnosis is po ssible. depending on the load condition, either a fault current i is(fault) or an open load in off current i is(oloff) may be present at is pin. in such situation, the current consumption of the device is increased. 6.1.5 active mode active mode is the normal operation mode of BTS7040-2EPA. the device enters active mode as soon as one in pin is set to ?high?. device curr ent consumption is specified with i gnd(active) (measured at gnd pin because the current at vs pin includes the lo ad current). overload, overtemperat ure and overvoltage protections are active. diagnosis is available. 6.2 undervoltage on v s between v s(op) and v s(uv) the undervoltage mechanism is triggered. if the device is operative (in active mode) and the supply voltage drops be low the undervoltage threshold v s(uv) , the internal logic switches off the output channels. as soon as the supply voltage v s is above the operative threshold v s(op) , the channels having the corresponding input pin set to ?high? are switched on a gain. the restart is delayed with a time t delay(uv) which protects the device in case the undervoltage co ndition is caused by a short circui t event (according to aec-q100-012), as shown in figure 14 . table 8 device function in relation to operation modes and v s voltage operative mode function v s in undervoltage v s not in undervoltage sleep channels off off diagnosis off off active channels off available diagnosis off available in off and on states stand-by channels off off diagnosis off available in off state data sheet 18 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power supply if the device is in sleep mode and one input is set to ?high?, the corresponding channel is switched on if v s > v s(op) without waiting for t delay(uv) . figure 14 v s undervoltage behavior powersupply_uvrvs.emf t v s(op) v s(uv) v s(hys) t v out v s t delay(uv) channel activation signal t data sheet 19 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power supply 6.3 electrical characteristics power supply v s = 6 v to 18 v, t j = -40 c to +150 c typical values: v s = 13.5 v, t j = 25 c typical resistive loads connected to the out puts for testing (unless otherwise specified): r l = 3.3 6.4 electrical characteristics power supply - product specific 6.4.1 BTS7040-2EPA table 9 electrical characteri stics: power supply - general parameter symbol values unit note or test condition number min. typ. max. vs pin power supply undervoltage shutdown v s(uv) 1.8 2.3 3.1 v v s decreasing in = ?high? from v ds 0.5 v to v ds = v s see figure 14 p_6.4.0.1 power supply minimum operating voltage v s(op) 2.0 3.0 4.1 v v s increasing in = ?high? from v ds = v s to v ds 0.5 v see figure 14 p_6.4.0.3 power supply undervoltage shutdown hysteresis v s(hys) ?0.7?v 1) v s(op) - v s(uv) see figure 14 1) not subject to production test - specified by design p_6.4.0.6 power supply undervoltage recovery time t delay(uv) 2.5 5 7.5 ms d v s /d t 0.5 v/s v s -1 v see figure 14 p_6.4.0.7 breakdown voltage between gnd and vs pins in reverse battery -v s(rev) 16 ? 30 v 1) i gnd(rev) = 7 ma t j = 150 c p_6.4.0.9 data sheet 20 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power supply table 10 electrical characterist ics: power supply BTS7040-2EPA parameter symbol values unit note or test condition number min. typ. max. power supply current consumption in sleep mode with loads at t j 85 c i vs(sleep)_85 ?0.030.5a 1) v s = 18 v v out = 0 v in = den = ?low? t j 85 c 1) not subject to production test - specified by design p_6.5.6.1 power supply current consumption in sleep mode with loads at t j = 150 c i vs(sleep)_150 ?3.514a v s = 18 v v out = 0 v in = den = ?low? t j = 150 c p_6.5.6.2 operating current in active mode (all channels on) i gnd(active) ?34ma v s = 18 v in = den = ?high? p_6.5.6.3 operating current in stand- by mode i gnd(stby) ?1.21.8ma v s = 18 v in = ?low? den = ?high? p_6.5.6.5 data sheet 21 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power stages 7 power stages the high-side power stages are built using a n-ch annel vertical power mo sfet with charge pump. 7.1 output on-state resistance the on-state resistance r ds(on) depends mainly on junction temperature t j . figure 15 shows the variation of r ds(on) across the whole t j range. the value ?2? on the y- axis corresponds to the maximum r ds(on) measured at t j = 150 c. figure 15 r ds(on) variation factor the behavior in reverse polarity is described in chapter 8.4.1 . 7.2 switching loads 7.2.1 switching resistive loads when switching resistive loads, the sw itching times and slew rates shown in figure 16 can be considered. the switch energy values e on and e off are proportional to load resistance and times t on and t off . 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 -40-30-20-100 102030405060708090100110120130140150160 r d s ( o n ) v a r i a t i o n f a c t o r j u n c t i o n t e m p e r a t u r e ( c ) r d s ( o n ) v a r i a t i o n o v e r t j typical reference value: " 2 " = r d s ( o n ) , m a x @ 1 5 0 c data sheet 22 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power stages figure 16 switching a resistive load 7.2.2 switching inductive loads when switching off inductive loads wi th high-side switches, the voltage v out drops below ground potential, because the inductance intends to co ntinue driving the current . to prevent the destruction of the device due to overvoltage, a voltage clamp mechanism is implem ented. the clamping structure limits the negative output voltage so that v ds = v ds(clamp) . figure 17 shows a concept drawing of the implementation. the clamping structure protects the device in all operation modes listed in chapter 6.1 . figure 17 output clamp concept in t v out v in(th) (d v /d t) on v in(hys) p dmos t t power st age_switchres.emf e on e off t on t on(delay) t off(delay) -(d v /d t) off t off 10% of v s 90% of v s 70% of v s 30% of v s 30% of v s 70% of v s power st age_clamp_intdio.emf high-side channel v s l , r l v outn i l v ds (clamp) i l vs out n v ds gnd v s(clamp) is v is (cl a m p) r sense r gn d data sheet 23 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power stages during demagnetization of inductive loads, energy has to be dissipated in BTS7040-2EPA. the energy can be calculated with equation (7.1) : (7.1) the maximum energy, therefore the maxi mum inductance for a given current, is limited by the thermal design of the component. 7.2.3 output voltage limitation to increase the current sense accuracy, v ds voltage is monitored. when the output current i l decreases while the channel is diagnosed (den pin set to ?high?, channel selected with dsel pins - see figure 18 ) bringing v ds equal or lower than v ds(slc) , the output dmos gate is partially discha rged. this increases the output resistance so that v ds = v ds(slc) even for very small output currents. the v ds increase allows the cu rrent sensing circuitry to work more efficien tly, providing better k ilis accuracy for output current in the low range. figure 18 output voltage limitati on activation during diagnosis 7.3 advanced switching characteristics 7.3.1 inverse current behavior when v out > v s , a current i inv flows into the power output transistor (see figure 19 ). this condition is known as ?inverse current?. if the channel is in off state, the current flows through the intrinsic body diode generating high power losses therefore an increase of overall device temperature. this may lead to a switch off of unaffected channels due to overtemperature. if the channel is in on state, r ds(inv) can be expected and power dissipation in the output stage is comparable to normal operation in r ds(on) . during inverse current condition, the channe l remains in on or of f state as long as i inv < i l(inv) . if one channel has inverse current applied, the ne ighbor channel is not influenced, meaning that switching on and off timings, protection (overcurrent, ov ertemperature) and current sensing ( k ilis ) are still within specified limits. ev ds clamp ?? v s v ds clamp ?? ? r l ---------------------- --------------------- - 1 r l i ? l v s v ds clamp ?? ? ---------------- -------------- ------------- - ? ?? ?? i l + ln ? l r l ------ ?? = in i l t t power st age_gbr_dia g.emf t den t sis(on) t sis(off) t v ds v ds(slc) v s data sheet 24 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power stages with inverseon, it is possible to switch on the channel during inve rse current condition as long as i inv < i l(inv) (see figure 20 ). figure 19 inverse current circuitry figure 20 inverseon - channel behavior in case of applied inverse current out v s v bat i inv inv comp. v inv = v out > v s gate driver device logic gnd power st age_inv curr_intdio.emf r gnd off off case 2 : switch is off in t i l t dmos state t inverse normal normal on inverse normal i l t dmos state t on case 1 : switch is on in t normal off on case 4 : switch off into inverse current in t i l t dmos state t inverse normal normal on inverse normal i l t dmos state t off case 3 : switch on into inverse current in t normal off on on off powerstage_invcurr_invon.emf data sheet 25 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power stages note: no protection mechanism like overtemperature or overload protec tion is active during applied inverse currents. 7.3.2 switching channels in parallel in case of appearance of a short circuit with connected in parallel to drive a single load, it may happen that the two channels switch off asynchronously, therefore bringi ng an additional thermal stress to the channel that switches off last. for this reason it is not recommended to use the device with channels in parallel. 7.3.3 cross current robustness with h-bridge configuration when BTS7040-2EPA is used as high-side switch e.g. in a bridge configuration (there fore paired with a low-side switch as shown in figure 21 ), the maximum slew rate ap plied to the output by the low-side switch must be lower than | d v out / d t |. otherwise the output stage may turn on in linear mode (not in r ds(on) ) while the low- side switch is commutating. this cr eates an unprotected over heating situ ation for the dmos due to the cross- conduction current. figure 21 high-side switch used in bridge configuration in0 in1 out0 out1 vs power st age_passive sl ew_profe t.em f t t v bat r/l cable m on (dc) off on (pwm) off current through motor cross current | d v out / d t | data sheet 26 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power stages 7.4 electrical characteristics power stages v s = 6 v to 18 v, t j = -40 c to +150 c typical values: v s = 13.5 v, t j = 25 c typical resistive loads connected to the out puts for testing (unless otherwise specified): r l = 3.3 7.4.1 electrical characteristics power stages - profet table 11 electrical characterist ics: power stages - general parameter symbol values unit note or test condition number min. typ. max. voltages drain to source clamping voltage at t j = -40 c v ds(clamp)_-40 33 36.5 42 v i l = 5 ma t j = -40c see figure 17 p_7.4.0.1 drain to source clamping voltage at t j 25 c v ds(clamp)_25 35 38 44 v 1) i l = 5 ma t j 25c see figure 17 1) tested at t j = 150c p_7.4.0.2 table 12 electrical characterist ics: power stages - profet parameter symbol values unit note or test condition number min. typ. max. timings switch-on delay t on(delay) 10 35 60 s v s = 13.5 v v out = 10% v s see figure 16 p_7.4.1.1 switch-off delay t off(delay) 10 25 50 s v s = 13.5 v v out = 90% v s see figure 16 p_7.4.1.2 switch-on time t on 30 60 110 s v s = 13.5 v v out = 90% v s see figure 16 p_7.4.1.3 switch-off time t off 15 50 100 s v s = 13.5 v v out = 10% v s see figure 16 p_7.4.1.4 switch-on/off matching t on - t off t sw -20 20 60 s v s = 13.5 v p_7.4.1.5 voltage slope data sheet 27 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power stages 7.5 electrical characteristics - power output stages 7.5.1 power output stage - 40 m switch-on slew rate (d v /d t ) on 0.3 0.6 0.9 v/ s v s = 13.5 v v out = 30% to 70% of v s see figure 16 p_7.4.1.6 switch-off slew rate -(d v /d t ) off 0.3 0.6 0.9 v/ s v s = 13.5 v v out = 70% to 30% of v s see figure 16 p_7.4.1.7 slew rate matching (d v /d t ) on - (d v /d t ) off (d v /d t ) sw -0.15 0 0.15 v/ s v s = 13.5 v p_7.4.1.8 voltages output voltage drop limitation at small load currents v ds(slc) 2718mv 1) den = ?high? channel selected with dsel pin i l = i l(ol) = 20 ma see figure 18 p_7.4.1.9 1) not subject to production test - specified by design table 13 electrical characteri stics: power stages - 40 m parameter symbol values unit note or test condition number min. typ. max. output characteristics on-state resistance at t j =25c r ds(on)_25 ?19?m 1) t j = 25 c p_7.5.6.1 on-state resistance at t j = 150 c r ds(on)_150 ??36m t j = 150 c i l = 2 a p_7.5.6.2 on-state resistance in cranking r ds(on)_cran k ??45m t j = 150 c v s = 3.1 v i l = 0.75 a p_7.5.6.3 on-state resistance in inverse current at t j = 25 c r ds(inv)_25 ?21?m 1) t j = 25 c v s = 13.5 v i l = -2 a p_7.5.6.4 table 12 electrical characterist ics: power stages - profet (continued) parameter symbol values unit note or test condition number min. typ. max. data sheet 28 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 power stages on-state resistance in inverse current at t j = 150 c r ds(inv)_150 ??45m t j = 150 c v s = 13.5 v i l = -2 a p_7.5.6.5 on-state resistance in reverse polarity at t j = 25 c r ds(rev)_25 ?21?m 1) t j = 25 c v s = -13.5 v i l = -2 a r sense = 1.2 k p_7.5.6.6 on-state resistance in reverse polarity at t j = 150 c r ds(rev)_150 ??74m t j = 150 c v s = -13.5 v i l = -2 a r sense = 1.2 k p_7.5.6.7 nominal load current per channel (all channels active) i l(nom) ?3.5?a 1) t a = 85 c t j 150 c p_7.5.6.8 output leakage current at t j 85 c i l(off)_85 ?0.010.5 a 1) v out = 0 v v in = ?low? t a 85 c p_7.5.6.9 output leakage current at t j = 150 c i l(off)_150 ?1.24 a v out = 0 v v in = ?low? t a = 150 c p_7.5.6.10 inverse current capability i l(inv) ?3.5?a 1) v s < v out in = ?high? p_7.5.6.11 voltage slope passive slew rate (e.g. for half bridge configuration) |d v out / d t |? ? 10 v/ s 1) v s = 13.5 v p_7.5.6.12 voltages drain source diode voltage | v ds(diode) | ? 650 700 mv i l = -190 ma t j = 150 c p_7.5.6.13 switch-on energy e on ?0.44?mj 1) v s = 18 v p_7.5.6.14 switch-off energy e off ?0.55?mj 1) v s = 18 v p_7.5.6.15 1) not subject to production test - specified by design table 13 electrical characteri stics: power stages - 40 m (continued) parameter symbol values unit note or test condition number min. typ. max. data sheet 29 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection 8 protection the BTS7040-2EPA is protected agains t overtemperature, overload, reve rse battery (with reversave?) and overvoltage. overtemperature and over load protections are working when the device is not in sleep mode. overvoltage protection works in all operation modes. reverse battery pr otection works when the gnd and vs pins are reverse supplied. 8.1 overtemperature protection the device incorporates both an absolute ( t j(abs) ) and a dynamic ( t j(dyn) ) temperature protection circuitry for each channel. an increase of junction temperature t j above either one of the two thresholds ( t j(abs) or t j(dyn) ) switches off the overheated channe l to prevent destruction. the ch annel remains switched off until junction temperature has reached the ?restart? condition described in table 14 . the behavior is shown in figure 22 (absolute overtemperature protection) and figure 23 (dynamic overtemperature protection). t j(ref) is the reference temperature used for dynamic temperature protection. figure 22 overtemperature protection (absolute) i l(ovl) i l t t j i is protection_profet_ot_irc.emf den in ter nal count er t j(abs) t t t t 1 0 in t i is(sat) i is(faul t) t hys(abs) t is(faul t)_d i l / k ilis data sheet 30 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection figure 23 overtemperature protection (dynamic) when the overtemperature protection ci rcuitry allows the channel to be sw itched on again, the retry strategy described in chapter 8.3 is followed. 8.2 overload protection the BTS7040-2EPA is protected in case of overload or short circuit to ground. two overload thresholds are defined (see figure 24 ) and selected automatically depending on the voltage v ds across the power dmos: ? i l(ovl0) when v ds < 13 v ? i l(ovl1) when v ds > 22 v i l(ovl) i l t t j i is protection_profet_dt_irc.emf den in ter nal count er t j(abs) t t t t 1 0 in t i is(faul t) t j(dyn) t is(faul t)_d i l / k ilis t j(ref) 2 data sheet 31 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection figure 24 overload current thresholds variation with v ds in order to allow a higher load inrush at low ambien t temperature, overload th reshold is maximum at low temperature and decreases when t j increases (see figure 25 ). i l(ovl0) typical value remains constant up to a junction temperature of +75 c. figure 25 overload current thresholds variation with t j 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 4 6 8 10 12 14 16 18 20 22 24 26 28 d r a i n s o u r c e v o l t a g e ( v ) o v e r l o a d t h r e s h o l d v a r i a t i o n ( " 1 " = i l ( o v l ) t y p @ v d s = 5 v ) i l ( o v l 0 ) i l ( o v l 1 ) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 -40 -20 0 20 40 60 80 100 120 140 160 i l ( o v l 0 ) v a r i a t i o n f a c t o r j u n c t i o n t e m p e r a t u r e ( c ) i l ( o v l 0 ) v a r i a t i o n o v e r t j typ reference value " 1 " = i l ( o v l 0 ) t y p @ - 4 0 c data sheet 32 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection power supply voltage v s can increase above 18 v for short time, for instance in load dump or in jump start condition. whenever v s v s(js) , the overload detection current is set to i l(ovl_js) as shown in figure 26 . figure 26 overload detection current variation with v s voltage when i l i l(ovl) (either i l(ovl0) or i l(ovl1) ), the channel is switched off. the channel is allowed to restart according to the retry strategy described in chapter 8.3 . 8.3 protection and diagnosis in case of fault any event that triggers a protecti on mechanism (either overtemperatur e or overload) ha s 2 consequences: ? the affected channel switches off and the internal counter is incremented ? if the diagnosis is active for the affected channel, a current i is(fault) is provided by is pin (see chapter 9.2.2 for further details) the channel can be switched on again if all the pr otection mechanisms fulfi ll the ?restart? conditions described in table 14 . furthermore, the device has an internal retry counter (one for each channel) to maximize the robustness in case of fault. 8.3.1 retry strategy when in is set to ?high?, the channe l is switched on. in case of fault condition the output stage is switched off. the channel can be allowed to re start only if the ?resta rt? conditions for the pr otection mechanisms are fulfilled (see table 14 ). table 14 protection ?restart? condition fault condition switch off event ?restart? condition overtemperature t j t j(abs) or ( t j - t j(ref) ) t j(dyn) t j < t j(abs) and ( t j - t j(ref) ) < t j(dyn) (including hysteresis) overload i l i l(ovl) i l < 50 ma t j within t j(abs) and t j(dyn) ranges (including hysteresis) protecti o n_js .emf i l(ovl ) v s v s(js) i l(ovl_ js) data sheet 33 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection the channel is allowed to switch on for n retry(cr) times before switching off. after a time t retry , if the input pin is set to ?high?, the cha nnel switches on again for n retry(nt) times before switching off again (?retry? cycle). after n retry(cyc) consecutive ?retry? cycles, the ch annel latches off. it is necessary to set the input pin to ?low? for a time longer than t delay(cr) to de-latch the channel (?counter rese t delay? time) and to reset the internal counter to the default value. during the ?counter reset delay? time , if the input is set to ?high? the channel remains swit ched off and the timer counting t delay(cr) is reset, starting to count again as soon as the input pin is set to ?low? again. if the input pin remains ?low? fo r a time longer than t delay(cr) the internal retry counter is reset to the default value, allowing n retry(cr) retries at the next channel activation. the retry strategy is shown in figure 29 (flowchart), figure 27 (timing diagram - input pin always ?high?) and figure 28 (timing diagram - channel controlled in pwm). figure 27 retry strategy timing diagram figure 28 retry strategy timing di agram - channel operated in pwm t in t retry short circu it to ground i l 0 1 n retry(cr) in ter nal count er n retry(cr) + n retry(nt) n retry(cr) + (n retry(cyc) * n retry(nt) ) t delay(cr) t retry 0 n retry(cr) n retry(nt) "retry" cycle n retry(nt) t t t protection_profet_time_nopwm.emf n retry(cyc) t den t i is i is(faul t) i l / k ilis i l / k ilis t in t retry short circu it to ground i l 0 1 n retry(cr) in ter nal count er n retry(cr) + n retry(nt) n retry(cr) + (n retry(cyc) * n retry(nt) ) t delay(cr) t retry 0 n retry(cr) n retry(nt) "retry" cycle n retry(nt) t t t protection_profet_timings.emf n retry(cyc) data sheet 34 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection figure 29 retry strategy flowchart protection_profet_flow.emf fault (overtemperature or overload) switch channel on no channel remains on switch channel off yes counter++ in is "high" yes channel remains off yes "retry" cycles = n retry(cyc) no wa it for t retry "retry" cycles++ yes wa it until in is "low" the n start counting for t del ay (cr) in is "low" t de l ay (cr) elapsed continue counting for t de l ay (cr) yes no no yes counter = 0 "retry" cycles = 0 counter < n retry(cr) no "retry" cycles = n retry(cyc) yes yes in is "high" yes switch channel off no start no all "restart" conditions fulfilled no no data sheet 35 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection it is possible to ?force? a reset of th e internal counter without waiting for t delay(cr) by applying a pulse (rising edge followed by a falling edge) to the den pin while in pin is ?low?. the pulse applied to den pin must have a duration longer than t den(cr) to ensure a reset of the internal counte r. the dsel pin must select the channel that has to be de-latched and keep the same logic value while den pi n toggles twice (risin g edge followed by a falling edge). the timings are shown in figure 30 . figure 30 retry strategy timing diagram with forced reset 8.4 additional protections 8.4.1 reverse polarity protection in reverse polarity condition (also known as revers e battery), the output stages are switched on (see parameter r ds(rev) ) because of reversave? featur e which limits the power dissip ation in the output stages. each esd diode of the logic contributes to total powe r dissipation. the reverse current through the output stages must be limited by the connected loads. the curren t through digital input pins has to be limited as well by an external resistor (please refer to the absolute maximum ratings listed in chapter 4.1 and to application information in chapter 10 ). figure 31 shows a typical application incl uding a device with reversave?. a current flowing into gnd pin (- i gnd ) during reverse polarity condition is necessary to activate reversave?, therefore a resistive path between module ground and device gnd pin must be present. t in short circu it to ground i l 0 1 in ter nal count er n retry(cr) t t t protection_profet_denforce_time2.emf den n retry(cr) 1 t t den(cr) 0 t den(cr) n retry(cr) t den(cr) n retry(cr) 0 data sheet 36 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection figure 31 reverse battery protection (application example) 8.4.2 overvoltage protection in the case of supply voltages between v s(ext,up) and v bat(ld) , the output transistors are still operational and follow the input pin. in additi on to the output clamp for inductive loads as described in chapter 7.2.2 , there is a clamp mechanism available for ov ervoltage protection for the logic and the output channels, monitoring the voltage between vs and gnd pins ( v s(clamp) ). 8.5 protection against loss of connection 8.5.1 loss of battery and loss of load the loss of connection to battery or to the load has no influence on device robustness when load and wire harness are purely resistive. in case of driving an inductive lo ad, the energy stored in the inductance must be handled. profet tm +2 devices can handle the inductivity of the wire harness up to 10 h with i l(nom) . in case of applications where currents and/or the aforementioned inductivit y are exceeded, an external suppressor diode (like diode d z2 shown in chapter 10 ) is recommended to handle the energy and to provide a well- defined path to the load current. 8.5.2 loss of ground in case of loss of module ground with the load rema ining connected to ground, th e device protects itself by automatically switching off (when it was previously on) or re mains off, regardless of the voltage applied on in pins. in case of loss of device ground, it is recommended to have a resistor connected between any digital input pin and the micro controller to ensure a channel switch off (as described in chapter 10 ). protection_revbatt.emf high-side channel l, c, r vs outn gnd is r se nse r gnd reversave tm di micro controller do r di gnd -i l -i gnd -i is i di -v bat(rev) data sheet 37 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection 8.6 electrical characteristics protection v s = 6 v to 18 v, t j = -40 c to +150 c typical values: v s = 13.5 v, t j = 25 c typical resistive loads connected to the out puts for testing (unless otherwise specified): r l = 3.3 8.6.1 electrical characteristics protection table 15 electrical characteri stics: protection - general parameter symbol values unit note or test condition number min. typ. max. thermal shutdown temperature (absolute) t j(abs) 150 175 200 c 1)2) see figure 22 1) functional test only 2) tested at t j = 150c only p_8.6.0.1 thermal shutdown hysteresis (absolute) t hys(abs) ?30?k 3) see figure 22 3) not subject to production test - specified by design p_8.6.0.2 thermal shutdown temperature (dynamic) t j(dyn) ?80?k 3) see figure 23 p_8.6.0.3 power supply clamping voltage at t j = -40 c v s(clamp)_-40 33 36.5 42 v i vs = 5 ma t j = -40 c see figure 17 p_8.6.0.6 power supply clamping voltage at t j 25 c v s(clamp)_25 35 38 44 v 2) i vs = 5 ma t j 25 c see figure 17 p_8.6.0.7 power supply voltage threshold for overcurrent threshold reduction in case of short circuit v s(js) 20.5 22.5 24.5 v 3) setup acc. to aec- q100-012 p_8.6.0.8 table 16 electrical characteristics: protection parameter symbol values unit note or test condition number min. typ. max. automatic retries in case of fault after a counter reset n retry(cr) ?5? 1) see figure 27 and figure 28 p_8.6.1.1 automatic retries in case of fault after the first t retry activation n retry(nt) ?1? 1) see figure 27 and figure 28 p_8.6.1.3 maximum ?retry? cycles allowed before channel latch off n retry(cyc) ?2? 1) see figure 27 and figure 28 p_8.6.1.4 data sheet 38 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 protection 8.7 electrical characteristics pr otection - power output stages 8.7.1 protection power output stage - 40 m auto retry time after fault condition t retry 40 70 100 ms 1) see figure 27 and figure 28 p_8.6.1.5 counter reset delay time after fault condition t delay(cr) 40 70 100 ms 1) see figure 27 and figure 28 p_8.6.1.6 minimum den pulse duration for counter reset t den(cr) 50 100 150 s 2) see figure 30 p_8.6.1.7 1) functional test only 2) not subject to production test - specified by design table 17 electrical characteri stics: protection - 40 m parameter symbol values unit note or test condition number min. typ. max. overload detection current at t j = -40 c i l(ovl0)_-40 42 47 52 a 1) t j = -40 c d i /d t = 0.2 a/s see figure 24 1) functional test only p_8.7.6.1 overload detection current at t j = 25 c i l(ovl0)_25 40 46 52 a 2) t j = 25 c d i /d t = 0.2 a/s see figure 24 2) not subject to production test - specified by design p_8.7.6.7 overload detection current at t j = 150 c i l(ovl0)_150 34 39 45 a 2) t j = 150 c d i /d t = 0.2 a/s see figure 24 p_8.7.6.8 overload detection current at high v ds i l(ovl1) ?26?a 2) d i /d t = 0.2 a/s see figure 24 p_8.7.6.5 overload detection current jump start condition i l(ovl_js) ?26?a 2) v s > v s(js) d i /d t = 0.2 a/s p_8.7.6.6 table 16 electrical characteristics: protection (continued) parameter symbol values unit note or test condition number min. typ. max. data sheet 39 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis 9 diagnosis for diagnosis purpose, the BTS7040-2EPA provides a combination of digital an d analog signals at pin is. these signals are generically named sense and written i is . in case of disabled diagnostic (den pin set to ?low?), is pin becomes high impedance. a sense resistor r sense must be connected between is pin and modu le ground if the curr ent sense diagnosis is used. r sense value has to be higher than 820 (or 400 when a central reverse battery protection is present on the battery feed) to limit the power losses in the sense circuitry. a typical value is r sense = 1.2 k . due to the internal connection between is pin and v s supply voltage, it is not recommended to connect the is pin to the sense current output of other devices, if they are supp lied by a differ ent battery feed. see figure 32 for details as an overview. figure 32 diagnosis block diagram 9.1 overview table 18 gives a quick reference for the state of the is pin during BTS7040-2EPA operation. channel 1 diagnosis_profet_2ch.emf is pin control logic internal counters inn dsel den overtemperature i is(fault) out0 vs mux v ds(oloff) i is(oloff) mux is r sen se out1 mux + channel 0 t i l / k ilis data sheet 40 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis 9.1.1 sense signal truth table in case den is set to ?high?, the sense for the selected channel is enabled or disabled using dsel pin. table 19 gives the truth table. 9.2 diagnosis in on state a current proportional to the load current (ratio k ilis = i l / i is ) is provided at pin is when the following conditions are fulfilled: table 18 sense signal, function of application condition application condition input level den level v out diagnostic output normal operation ?low? ?high? ~ gnd z i is(fault) if counter > 0 short circuit to gnd ~ gnd z i is(fault) if counter > 0 overtemperature z i is(fault) short circuit to v s v s i is(oloff) ( i is(fault) if counter > 0) open load < v s - v ds(oloff) > v s - v ds(oloff) 1) 1) with additional pull-up resistor z i is(oloff) (in both cases i is(fault) if counter > 0) inverse current ~ v inv = v out > v s i is(oloff) ( i is(fault) if counter > 0) normal operation ?high? ~ v s i is = i l / k ilis overcurrent < v s i is(fault) short circuit to gnd ~ gnd i is(fault) overtemperature z i is(fault) short circuit to v s v s i is < i l / k ilis open load ~ v s 2) 2) the output current ha s to be smaller than i l(ol) i is = i is(en) under load (e.g. output voltage limitation condition) ~ v s 3) 3) the output current has to be higher than i l(ol) i is(en) < i is < i l(nom) / k ilis inverse current ~ v inv = v out > v s i is = i is(en) all conditions n.a. ?low? n.a. z table 19 diagnostic truth table den dsel is ?low? not relevant z ?high? ?low? sense output 0 ?high? ?high? sense output 1 data sheet 41 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis ? the power output stage is switched on with v ds < 2 v ? the diagnosis is enabled for that channel ? no fault (as described in chapter 8.3 ) is present or was present and not cleared yet (see chapter 9.2.2 for further details) if a ?hard? failure mode is present or was present and not cleared yet a current i is(fault) is provided at is pin. 9.2.1 current sense ( k ilis ) the accuracy of the sense current depe nds on temperature and load current. i is increases linearly with i l output current until it reac hes the saturation current i is(sat) . in case of open load at the output stage ( i l close to 0 a), the maximum sense current i is(en) (no load, diagnosis enabled) is sp ecified. this condition is shown in figure 34 . the blue line represents the ideal k ilis line, while the red lines show the behavior of a typical product. an external rc filter between is pin and micro controlle r adc input pin is recommended to reduce signal ripple and oscillations (a minimum time constant of 1 s for the rc filter is recommended). the k ilis factor is specified with limits that take into ac count effects due to temper ature, supply voltage and manufacturing process. tighter limits are possible (within a defined current window) with calibration: ? a well-defined and precise current ( i l(cal) ) is applied at the output during end of line test at customer side ? the corresponding current at is pin is measured and the k ilis is calculated ( k ilis @ i l(cal) ) ? within the current range going from i l(cal)_l to i l(cal)_h the k ilis is equal to k ilis @ i l(cal) with limits defined by k ilis the derating of k ilis after calibration is calculated using the formulas in figure 33 and it is specified by k ilis figure 33 k ilis calculation formulas the calibration is intended to be performed at t a(cal) = 25c. the parameter k ilis includes the drift over temperature as well as the drif t over the current range from i l(cal)_l to i l(cal)_h . figure 34 current sense ratio in open load at on condition diagnosis_dkilis.emf i is i l i l(ol) i is(ol ) di agn o si s_ olon _adv .em f i is(en) data sheet 42 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis 9.2.2 fault current ( i is(fault) ) as soon a protection event occurs, changing the value of the intern al retry counter (see chapter 8.3 for more details) from its re set state, a current i is(fault) is provided by pin is when den is set to ?high? and the affected channel is selected. the following 3 situations may occur: ? if the channel is on and the numb er of retries is lower than ? n retry(cr) + n retry(cyc) * n retry(nt) ?, the current i is(fault) is provided for a time t is(fault)_d after the channel is allowed to restart, after which i is = i l / k ilis (as shown in figure 35 ). during a retry cycle (while timer t retry is running) the current i is(fault) is provided each time the channel diagnosis is checked ? if the channel is on and the numb er of retries is equal than ? n retry(cr) + n retry(cyc) * n retry(nt) ?, the current i is(fault) is provided until the internal coun ter is reset (either by expiring of t delay(cr) time or by den pin pulse, as described in chapter 8.3.1 ) ? if the channel is off and the internal coun ter is not in the reset state, the current i is(fault) is provided each time the channel diagnosis is checked figure 35 i is(fault) at load switching figure 36 adds the behavior of sense signal to the timing diagram seen in figure 28 , while figure 37 shows the relation between i is = i l / k ilis , i is(sat) and i is(fault) . t in i l 0 1 in ter nal count er t t diagnosis_profet_iisfaul t_load.emf t den t i is i is(faul t) i l / k ilis t is(faul t)_d 2 i is(faul t) 0 i l(ovl) data sheet 43 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis figure 36 sense behavior in fault condition figure 37 sense behavior - overview 9.3 diagnosis in off state when a power output stage is in off state, the bt s7040-2epa can measure the ou tput voltage and compare it with a threshold voltage. in this way, using some a dditional external components (a pull-down resistor and a switchable pull-up current source), it is possible to detect if the load is mi ssing or if there is a short circuit to battery. if a fault condition was detected by the device (the internal counter has a value different from the reset value, as described in chapter 9.2.2 ) a current i is(fault) is provided by is pin each time the channel diagnosis is checked also in off state. t in t retry short circu it to ground i l 0 1 n retry(cr) in ter nal count er n retry(cr) + n retry(nt) n retry(cr) + (n retry(cyc) * n retry(nt) ) t delay(cr) t retry 0 n retry(cr) n retry(nt) "retry" cy cle n retry(nt) t t t diagnosis_profet_iisfault.emf t den t i is i is(faul t) i is(faul t) i l / k ilis n retry(cyc) i is(faul t) di agnosis_profe t_iisfaul t_iiss at.emf i is i l i is(sat) i is(faul t) i l / k ilis i is(sa t),min = i is(faul t),min i is(faul t),max i is(sa t),max i l(ovl) data sheet 44 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis 9.3.1 open load current ( i is(oloff) ) in off state, when den pin is set to ?high? and a channel is selected using dsel pin, the v ds voltage is compared with a threshold voltage v ds(oloff) . if the load is properly connecte d and there is no short circuit to battery, v ds ~ v s therefore v ds > v ds(oloff) . when the diagnosis is active and v ds v ds(oloff) , a current i is(oloff) is provided by is pin. figure 38 shows the relationship between i is(oloff) and i is(fault) as functions of v ds . the two currents do not overlap making always possible to differentiate between open load in off and fault condition. figure 38 i is in off state it is necessary to wait a time t is(oloff)_d between the falling edge of the inpu t pin and the sensing at pin is for open load in off diagnosis to allow th e internal comparator to settle. in figure 39 the timings for an open load detection are shown - the load is always disconnected. figure 39 open load in off timings - load disconnected di agn o s is_p rofe t_i i sol off .em f i is v ds i is(oloff) v ds(oloff) i is(fault) t in t den v out ~ v s t is(oloff)_d t i is(oloff) i is i is(ol) v ds(oloff) t diagnosis_profet_oloff_time.emf load conn ect ed data sheet 45 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis 9.4 sense timings figure 40 and figure 42 show the timing during settling t sis(on) and disabling t sis(off) of the sense (including the case of load change). as a proper signal cannot be established befo re the load current is stable (therefore before t on ), t sis(diag) = t sis(on) + t on . figure 40 sense settling / disabling timing figure 41 sense timing with small load current t t t i l i is den t on off off diagnose_profet_sense_timings.emf in t sis(di ag) t sis(lc) t sis(o ff) t sis(on) t sis(o ff) t off den t t t t on off in off di agno se_profe t_s ens e_ti mi ngs_s lc.em f t sis(on)_slc t sis(on) t sis(lc)_slc i l i is data sheet 46 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis figure 42 sense settling timing - channel change diagnose_profet_sense_timings_cc.emf dsel i is t t t i l1 t t si s(cc) t sis(o ff) den t sis(on) t si s(cc)_slc t i l0 i l(cal)_l i l(cal) i l(cal)_o l data sheet 47 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis 9.5 electrical characteristics diagnosis v s = 6 v to 18 v, t j = -40 c to +150 c typical values: v s = 13.5 v, t j = 25 c typical resistive loads connected to the out puts for testing (unless otherwise specified): r l = 3.3 table 20 electrical characteri stics: diagnosis - general parameter symbol values unit note or test condition number min. typ. max. sense saturation current i is(sat) 4.4 ? 15 ma 1) v s = 8 v to 18 v r sense = 1.2 k see figure 37 p_9.6.0.13 sense saturation current i is(sat) 4.1 ? 15 ma 1) v s = 6 v to 18 v r sense = 1.2 k see figure 37 p_9.6.0.14 sense leakage current when disabled i is(off) ?0.010.5aden = ?low? i l i l(nom) v is = 0 v p_9.6.0.2 sense leakage current when enabled at t j 85 c i is(en)_85 ?0.21a 1) t j 85 c den = ?high? i l = 0 a see figure 34 p_9.6.0.3 sense leakage current when enabled at t j = 150 c i is(en)_150 ?0.21a t j = 150 c den = ?high? i l = 0 a see figure 34 p_9.6.0.4 sense operative range for k ilis operation ( v s - v is ) v sis_k ?0.51v 1) v s = 6 v in = den = ?high? i l 1.2 * i l(nom) p_9.6.0.6 sense operative range for open load at off diagnosis ( v s - v is ) v sis_ol ?0.51v 1) v s = 6 v in = ?low? den = ?high? p_9.6.0.7 sense operative range for fault diagnosis ( v s - v is ) v sis_f ?0.51v 1) v s = 6 v in = ?low? den = ?high? counter > 0 p_9.6.0.8 data sheet 48 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis 9.5.1 electrical characteristics diagnosis power supply to is pin clamping voltage at t j =-40c v sis(clamp)_- 40 33 36.5 42 v i is = 1 ma t j = -40 c see figure 17 p_9.6.0.9 power supply to is pin clamping voltage at t j 25 c v sis(clamp)_25 35 38 44 v 2) i is = 1 ma t j 25 c see figure 17 p_9.6.0.10 1) not subject to production test - specified by design 2) tested at t j = 150c table 21 electrical characteristics: diagnosis parameter symbol values unit note or test condition number min. typ. max. sense fault current i is(fault) 4.4 5.5 10 ma see figure 37 and figure 38 p_9.6.1.1 sense open load in off current i is(oloff) 1.9 2.5 3.5 ma see figure 37 and figure 38 p_9.6.1.2 sense delay time at channel switch on after last fault condition t is(fault)_d ? 500 ? s 1) see figure 35 p_9.6.1.3 sense open load in off delay time t is(oloff)_d 30 70 120 s v ds < v ol(off) from in falling edge to i is = i s(oloff),min * 0.9 den = ?high? counter = 0 see figure 39 p_9.6.1.4 open load v ds detection threshold in off state v ds(oloff) 1.3 1.8 2.3 v see figure 38 p_9.6.1.5 sense settling time with nominal load current stable t sis(on) ?520s i l = i l(cal) from den rising edge to i is = i l / ( k ilis,max @ i l ) * 0.9 see figure 40 p_9.6.1.6 sense settling time with small load current stable t sis(on)_slc ??60s 1) i l = i l(cal)_ol from den rising edge to i is = i l / ( k ilis,max @ i l ) * 0.9 p_9.6.1.13 table 20 electrical characteri stics: diagnosis - general (continued) parameter symbol values unit note or test condition number min. typ. max. data sheet 49 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis 9.6 electrical characteristics diagnosis - power output stages 9.6.1 diagnosis power output stage - 40 m sense disable time t sis(off) ?520s 1) from den falling edge to i is = i is(off) see figure 40 p_9.6.1.8 sense settling time after load change t sis(lc) ?520s 1) from i l = i l(cal)_l to i l = i l(cal) (see k ilis(nom) ) see figure 40 p_9.6.1.9 sense settling time after load change with small load current t sis(lc)_slc ? 250 400 s 1) den = ?high? from load change to i is = i l / ( k ilis @ i l ) from i l(cal) to i l(cal)_ol p_9.6.1.14 sense settling time after channel change t sis(cc) ?520s 1) start channel: i l = i l(cal) end channel: i l = i l(cal)_l (see k ilis(nom) ) see figure 42 p_9.6.1.10 sense settling time after channel change with small load current t sis(cc)_slc ??60s 1) den = ?high? from dsel toggling to i is = i l / ( k ilis,min @ i l ) * 1.1 start channel: i l = i l(cal) end channel: i l = i l(cal)_ol (see k ilis(nom) and k ilis(ol) ) p_9.6.1.15 1) not subject to production test - specified by design table 21 electrical characteristics: diagnosis (continued) parameter symbol values unit note or test condition number min. typ. max. data sheet 50 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 diagnosis table 22 electrical characte ristics: diagnosis - 40 m parameter symbol values unit note or test condition number min. typ. max. open load output current at i is = 4 a i l(ol)_4u 1611ma i is = i is(ol) = 4 a p_9.7.6.1 current sense ratio at i l = i l02 k ilis02 -40% 1800 +40% i l02 = 20 ma p_9.7.6.6 current sense ratio at i l = i l04 k ilis04 -35% 1800 +35% i l04 = 50 ma p_9.7.6.8 current sense ratio at i l = i l05 k ilis05 -30% 1800 +30% i l05 = 100 ma p_9.7.6.9 current sense ratio at i l = i l08 k ilis08 -26% 1800 +26% i l08 = 250 ma p_9.7.6.12 current sense ratio at i l = i l11 k ilis11 -11% 1800 +11% i l11 = 1 a p_9.7.6.15 current sense ratio at i l = i l13 k ilis13 -6% 1800 +6% i l13 = 2 a p_9.7.6.17 current sense ratio at i l = i l15 k ilis15 -5% 1800 +5% i l15 = 4 a p_9.7.6.19 sense current derating with low current calibration k ilis(ol) -30 0 +30 % 1) i l(cal)_ol = i l04 i l(cal)_ol_h = i l05 i l(cal)_ol_l = i l02 t a(cal) = 25 c p_9.7.6.27 sense current derating with nominal current calibration k ilis(nom) -4 0 +4 % 1) i l(cal) = i l13 i l(cal)_h = i l15 i l(cal)_l = i l11 t a(cal) = 25 c 1) not subject to production test - specified by design p_9.7.6.29 data sheet 51 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 application information 10 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or wa rranty of a certain func tionality, condition or quality of the device. 10.1 application setup figure 43 bts7040-2ep a application diagram note: this is a very simplified example of an applicatio n circuit. the function must be verified in the real application. table 23 loads considered for reverse polarity setup (see p_4.1.0.5) output r ds(on),max @ t j = 150 c load connected 40 m 36 m p27w + r5w gpio gpio gpio gpio a/d in vss vdd micro contro ller in0 in1 den dsel is gnd out0 out1 vs v bat c sense d z1 r/l cable r/l cable r/l cable c out1 c out0 r in r in r de n r dsel r ad r is_prot r sense r gnd v dd r pd r pd c vs r ol t 1 d z2 app_2ch_li_intdio.emf data sheet 52 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 application information 10.2 external components 10.3 further application information ? please contact us for information regarding the pin fmea ? for further information you may contact http://www.infineon.com/ table 24 suggested component values reference value purpose r in 4.7 k protection of the micro controller during overvoltage and reverse polarity. necessary to switch off bts7040-2e pa output during loss of ground r den 4.7 k protection of the micro controller during overvoltage and reverse polarity. necessary to switch off bts7040-2e pa output during loss of ground r pd 47 k output polarization (pull-down). improves BTS7040-2EPA immunity to electromagnetic noise r ol 1.5 k output polarization (pull-up). ensure polarization of BTS7040-2EPA output during open load in off diagnosis c out 10 nf protection of BTS7040-2EPA ou tput during esd events and bci t 1 bc 807 switch the battery voltage for open load in off diagnosis c vs 68 nf filtering of voltage spikes on the battery line d z2 33 v z-diode suppressor diode protection during overvoltage and in ca se of loss of battery while driving an inductive load r sense 1.2 k sense resistor r is_prot 4.7 k protection during overvoltage, re verse polarity, loss of ground. value to be tuned according to micro controller specifications. d z1 7 v z-diode protection of micro controller during overvoltage r a/d 4.7 k protection of micro controller adc input during overvoltage, reverse polarity, loss of ground. value to be tuned according to micro controller specifications. c sense 220 pf sense signal filtering a time constant ( r a/d * c sense ) longer than 1 s is recommended. r gnd 47 (1/16 w) protection in case of overvoltag e and loss of battery while driving inductive loads data sheet 53 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 package outlines 11 package outlines figure 44 pg-tsdso-14-22 (thin (slim) dual small outline 14 pins) package outline figure 45 pg-tsdso-14-22 (thin (slim) dual small outline 14 pins) package pads and stencil , 1 ' ( ; ' 2 ( 6 1 2 7 , 1 & / 8 ' ( 3 / $ 6 7 , & 2 5 0 ( 7 $ / 3 5 2 7 5 8 6 , 2 1 2 ) 0 $ ; 3 ( 5 6 , ' ( ' $ 0 % $ 5 3 5 2 7 8 6 , 2 1 6 + $ / / % ( 0 $ ; , 0 8 0 0 0 7 2 7 $ / , 1 ( ; & ( 6 6 2 ) / ( $ ' : , ' 7 + 0 $ ; [ [ 6 7 $ 1 ' 2 ) ) & [ 0 $ 5 . , 1 * 6 ( $ 7 , 1 * 3 / $ 1 ( & 2 3 / $ 1 $ 5 , 7 < s s s r r s $ % ' $ % & ' s % 2 7 7 2 0 9 , ( : s & s ' $ % [ [ s * $ 8 * ( 3 / $ 1 ( $ / / ' , 0 ( 1 6 , 2 1 6 $ 5 ( , 1 8 1 , 7 6 0 0 7 + ( ' 5 $ : , 1 * , 6 , 1 & 2 0 3 / , $ 1 & ( : , 7 + , 6 2 3 5 2 - ( & 7 , 2 1 0 ( 7 + 2 ' > @ f r s s h u v r o g h u p d v n v w h q f l o d s h u w x u h v $ / / ' , 0 ( 1 6 , 2 1 6 $ 5 ( , 1 8 1 , 7 6 0 0 data sheet 54 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 package outlines green product (rohs compliant) to meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb -free soldering according to ipc/jedec j-std-020). for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm data sheet 55 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 revision history 12 revision history table 25 BTS7040-2EPA - list of changes revision changes 1.00 , 2017-08-24 data sheet available table of contents data sheet 56 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 block diagram and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 absolute maximum ratings - general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 absolute maximum ratings - power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2.1 power stage - 40 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4.1 pcb setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4.2 thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 input pins (inn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 diagnosis pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 electrical characteristics logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.1 unsupplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.2 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.3 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.4 stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.5 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 undervoltage on v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 electrical characteristics power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 electrical characteristics power supply - product specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4.1 BTS7040-2EPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2.1 switching resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2.2 switching inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2.3 output voltage limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 advanced switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3.1 inverse current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3.2 switching channels in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3.3 cross current robustness wi th h-bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 electrical characteristics power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4.1 electrical characteristics power stages - profet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 electrical characteristics - power output stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.5.1 power output stage - 40 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table of contents table of contents data sheet 57 rev. 1.00 2017-08-24 BTS7040-2EPA profet tm +2 8 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 protection and diagnosis in case of fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.3.1 retry strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.4 additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4.1 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4.2 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.5 protection against loss of connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.5.1 loss of battery and loss of load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.5.2 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6 electrical characteristics protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.6.1 electrical characteristics protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.7 electrical characteristics protection - power output stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.7.1 protection power output stage - 40 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.1 sense signal truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 diagnosis in on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.1 current sense ( k ilis ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.2 fault current ( i is(fault) ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.3 diagnosis in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.1 open load current ( i is(oloff) ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.4 sense timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.5 electrical characteristics diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5.1 electrical characteristics diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.6 electrical characteristics diagnosis - po wer output stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.6.1 diagnosis power output stage - 40 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1 application setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.2 external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.3 further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 trademarks all referenced product or service names and trademarks are the proper ty of their respective owners. edition 2017-08-24 published by infineon technologies ag 81726 munich, germany ? 2017 infineon technologies ag. all rights reserved. do you have a question about any aspect of this document? email: erratum@infineon.com document reference important notice the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("beschaffenheitsgarantie"). with respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. in addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of infineon technologies in customer's applications. the data contained in this document is exclusively intended for technically trained staff. it is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements products may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. except as otherwise explicitly approved by infineon technologies in a written document signed by authorized representatives of infineon technologies, infineon technologies? products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. please read the important notice and warnings at the end of this document |
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